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CLA80000 Series
High Density CMOS Gate Arrays
DS3820
ISSUE 2.1
July 1997
INTRODUCTION
The CLA80k gate array series from Zarlink Semiconductor offers advantages in speed and density over previous array series. Improvements in design combined with advances in simulation accuracy allow the implementation of complex systems in excess of 260,000 gates.
ARRAY SIZES
The CLA80k series comprises 9 base arrays and 22 variants ranging from 2816 to 513,136 array elements. The optimum array for your requirement may be selected from the tables below. Double Layer Metal Arrays (High Density Pads) Array type CLA81XXX CLA82XXX CLA83XXX CLA84XXX CLA85XXX CLA86XXX CLA87XXX Array elements 2816 8736 17920 30784 54720 100048 157872 Usable gates 1400 4260 8400 13600 22000 30000 48000 Total Pads 64 88 112 136 168 216 264
FEATURES
I I I I I I I I I I 0.7 (0.8 drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (optional 5V I/O, 3V core logic) Low skew clock distribution strategy Power and ground distribution grids Extensive range of package options
OVERVIEW
The gate array has a comprehensive cell library including RAM generators as well as JTAG circuits. CLA80k is Zarlink Semiconductor's seventh generation CMOS gate array product. The family consists of 22 arrays implemented on a proven 0.7m (0.8m drawn) process which offers two or three layer metal. Zarlink Semiconductor's Design Centres offer support on a variety of design routes customized to individual requirements. Zarlink supplies design kits for the major industry standard ASIC design tools and all kits support advanced nonlinear delay calculations essential for accurate simulation. Standard Density Pad Arrays are targeted for use in ceramic packaging and for those applications which require assembly in conformance with MIL STD 883.
Triple Layer Metal Arrays (High Density Pads) Array type CLT81XXX CLT82XXX CLT83XXX CLT84XXX CLT85XXX CLT86XXX CLT87XXX CLT88XXX CLT89XXX Array elements 2816 8736 17920 30784 54720 100048 157872 307568 513136 Usable gates 1680 5200 10700 18000 32500 58000 90000 170000 260000 Total pads 64 88 112 136 168 216 264 360 456
Standard Density Pad Arrays Array type MLA85XXX MLT85XXX MLA87XXX MLT87XXX MLT88XXX MLT89XXX Array elements 54720 54720 157872 157872 307568 513136 Usable gates 22000 32500 48000 90000 170000 260000 Total pads 144 144 232 232 312 384
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ARCHITECTURE Core cell
I Optimized structure for a variety of logic elements I Allows routing through cells for compact layout The basic unit from which all library functions are constructed is called an `array element'. An array element consists of two P-channel and two N-channel plus a small P-channel transistor. Two basic cell or array elements are illustrated in Figure 1. To achieve the required circuit function, logic designers use a set of cells. Each library component realizes a logic function, ranging in complexity from an inverter to a master-slave `D' flip-flop. A fixed metal interconnection of the transistors from one or more array elements implements the cell function. A design is specified in terms of cells, macros, modules and their interconnections, which are then simulated using one of the many supported design platforms. If a design uses only two layers of metal then a set of four masks is required. One for contacts, one for vias (connections between the metal layers) and two for metals. If a design uses three layer metal then six masks are required. One for contacts, two for vias and three for metals.
VDD Supply
P Trans
Shared Diffusion
N Trans
GND Supply
Array Element
Array Element
I/O ARRANGEMENT
I High density and standard density pads available I 4KV ESD and latchup immunity I Programmable slew rate control Around the outside of the array are I/O blocks and pads placed at the chip periphery. All arrays have wide power bus rings situated over the I/O blocks. The partition of the I/O cell is shown in Figure 2. For high density pad arrays three pads are placed every four I/O cells whilst for standard density array pads two pads are placed for every three I/O cells. Each I/O cell is divided into a number of sections allowing a wide variety of different I/O cells to be constructed. Each I/O block can be customized as an input, output or bidirectional I/O port. In addition any pad location can be used as a positive or negative supply pad. Electrostatic discharge protection (ESD) is built into the I/O cells. This protection can withstand in excess of 4kV. The structure is also highly resistant to latch-up due to the epitaxial substrate used in the process. Slew rate control is provided within the I/O cell structure to minimize supply noise transients. This is a useful feature in larger designs where multiple high drive outputs need to be switched simultaneously.
OP-VDD
Figure 1 Pair of array elements
IB-VDD Intermediate Buffers IB-GND OP-VDD Output Drivers
OP-GND
Bond Pads
Repeated Structure
Figure 2 High density pad spacing
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CLOCK AND POWER DISTRIBUTION
I Low skew clock distribution strategy I Power grid to minimize voltage drop In large complex designs working at high speed, on chip clock and power distribution is vital to successful operation of the design. Zarlink has a number of techniques to minimize potential problems which can occur with clocking and powering the chip.
This continued investment demonstrates Zarlink Semiconductor's commitment to providing state-of-the-art CMOS ASICS.
Clock Distribution
The clock distribution network must ensure that skew is minimized and that long term failure does not occur due to metal migration. Three solutions available from ZarlinkZarlink are:
Pre-driver Metal 2 Vertical Grid
Pad
RAM
Large buffer Balanced Tree Clock Grid Distributed clock buffer cells are supported for the CLA80k family to minimise clock skew effects across a die. The use of these cells is restricted to three layer metal designs. Each array size from CLT84 upwards has its own unique buffer cell (CLKB8*). Each of the cells occupy one I/O block but with the output drive distributed across the die. The clock signal is routed at layout either as a grid, ring or spine structure to maintain clock skew within acceptable limits. These clock buffer cells are entered in the circuit schematic at the top level of the and all registers and latches should be driven directly from the clock buffer output.
MACROCELL
Metal 3 Horizontal Grid
Figure 3 Example of distributed clock buffer using a grid structure
Power Distribution
The power distribution metal in the array must be designed to avoid excessive voltage drops and long term failure due to electromigration. Metal 1 VDD and VSS tracks pass through all the array cells. At regular intervals across the array the metal 1 supply rails are fed by vertical metal 2 straps. For designs using three layers of metal additional straps can be added in metal 3. Fig 4 shows a representation of the grid arrangement.
Metal 2 Vertical Grid
Pad
Horizontal metal 3 Grid
MANUFACTURING
I Computer aided manufacturing I Class 10 or better clean room conditions I Vibration free for reliable manufacture The CLA80k product is manufactured near Plymouth England in a purpose built factory for sub-micron process geometry. The factory uses the latest automated equipment for 6-inch wafers in vibration free class 10 clean room conditions. Computer Aided Manufacture in the above environment ensures production efficiency and the lowest possible defect level. In addition to the world class wafer facility there are excellent probe and final test areas equipped with the latest analog and digital testers.
Figure 4 Example of three layer metal power grid
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CELL LIBRARY
I Comprehensive range of cells I JTAG and Paracell libraries A comprehensive cell library is available for the CLA80k series. It contains libraries that may be used in specific applications areas such JTAG boundary scan.
Complex Gates
A2A2O2I O2O2A2I A2O2I O2A2I A2O3I O2A3I A3O2I O3A2I A2O2A2I O2A2O2I 2 2-IP AND's into 2-IP NOR gate 2 2-IP OR's into 2-IP NAND gate 2-IP AND gate into 2-IP NOR gate 2-IP OR gate into 2-IP NAND gate 2-IP AND gate into 3-IP NOR gate 2-IP OR gate into 3-IP NAND gate 3-IP AND gate into 2-IP NOR gate 3-IP OR gate into 2-IP NAND gate 2-IP AND gate into 2-IP OR gate into 2-IP NAND gate 2-IP OR gate into 2-IP AND gate into 2-IP NOR gate
Buffers and Inverters
BUFX3 BUFX7 DELAY INVX1 INVX2 INVX4 INVX6 INVX8 Non-inverting driver with x3 drive Non-inverting driver with x7 drive Timing delay Inverter Inverter with x2 drive Inverter with x4 drive Inverter with x6 drive Inverter with x8 drive
Exclusive ORs and Adders
EXOR EXNOR HADD FADD FADD2 Exclusive OR gate Exclusive NOR gate Half adder 1 bit full adder 2 bit full adder
NAND Gates
NAND2 NAND2X2 NAND3 NAND3X2 NAND4 NAND4X2 2 input NAND gate 2 input NAND gate with x2 drive 3 input NAND gate 3 input NAND gate with x2 drive 4 input NAND gate 4 input NAND gate with x2 drive
Multiplexers
MUX2TO1 MUX4TO1 MUX8TO1 2 to 1 multiplexer 4 to 1 multiplexer 8 to 1 multiplexer
NOR Gates
NOR2 NOR2X2 NOR3 NOR3X2 NOR4 NOR4X2 2 input NOR gate 2 input NOR gate with x2 drive 3 input NOR gate 3 input NOR gate with x2 drive 4 input NOR gate 4 input NOR gate with x2 drive
Tristate Drivers
BDRX4 BDRX8 BHOLD Tristate bus driver with x4 drive Tristate bus driver with x8 drive Tristate bus hold
Clock Drivers
Cell Name CLKP Cell Function Positive edge clock driver Positive edge clock driver with x2 drive Positive edge clock driver with x3 drive Negative edge clock driver Negative edge clock driver with x2 drive Negative edge clock driver with x3 drive
AND Gates
AND2 AND2X2 AND3 AND3X2 AND4 OR Gates OR2 OR2X2 OR3 OR3X2 OR4 2 input OR gate 2 input OR gate with x2 drive 3 input OR gate 3 input OR gate with x2 drive 4 input OR gate 2 input AND gate 2 input AND gate with x2 drive 3 input AND gate 3 input AND gate with x2 drive 4 input AND gate
CLKPX2 CLKPX3 CLKN CLKNX2 CLKNX3
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Clock Grid Drivers
CLKB84 CLKB85 CLKB86 CLKB87 CLKB88 CLKB89 Clock Grid Driver for CLT84000 Clock Grid Driver for CLT85000, MLT85000 Clock Grid Driver for CLT86000 Clock Grid Driver for CLT87000, MLT87000 Clock Grid Driver for CLT88000, MLT88000 Clock Grid Driver for CLT89000, MLT89000
Level Shifter Cells
DRV6 IBST1 IBST2 IBST3 IBTTL1 IBTTL2 IBCMOS1 IBLEVELS Multiple output driver cell CMOS schmitt trigger, 5 volt supply TTL schmitt trigger, 5 volt supply CMOS & TLL schmitt trigger, 3 volt supply TTL input: 5 volt supply TTL input: 3 volt supply CMOS input: 5 volt supply 3 volt to 5 volt signal interface
Latches
SRLATCH DL DLR BDL BDLR Set-Reset latch Data latch Data latch with reset Buffered data latch Buffered data latch with reset
Output Driver Controllers
IBCOP IBCOP3 IBTRID Controller for push-pull, open source, and open drain output driver Controller for push-pull, open source, and open drain output driver Controller for tristate output driver Controller for tristate output driver
Registers
DF DFRS MDF MDFRS SDF SDFR SDFRS SDFS SMDF SMDFRS BDF BDFRS BMDF BMDFRS Master-slave D-type flip-flop Master-slave D-type flip-flop with set and reset Multiplexed master-slave D-type flip-flop Multiplexed master-slave D-type flip-flop with set and reset Buffered clock master-slave D-type flip-flop Buffered clock master-slave D-type flip-flop with reset Buffered clock master-slave D-type flip-flop with set and reset Buffered clock master-slave D-type flip-flop with set Buffered clock multiplexed master-slave Dtype Flip-Flop Buffered clock multiplexed master-slave Dtype flip-flop with set and reset Buffered master-slave D-type flip-flop Buffered master-slave D-type flip-flop with set and reset Buffered multiplexed master-slave D-type flip-flop Buffered multiplexed master-slave D-type flip-flop with set and reset
IBTRID3
Output Driver Cells
OPT1 OPT2 OPT3 OPT6 OPT12 Small output driver Small output driver Small output driver Standard output driver Large output driver
CLA8PARA LIBRARY
SPRAM DPRAM Single port RAM register file Dual port RAM register file
CLA8JTAG LIBRARY
GGJTAP GGIDREG GGJTREG JTAG Interface Controller JTAG identification register JTAG boundary scan register
Oscillator Cells
OSC32K OSCHIGH OSCMID 32kHz Crystal Oscillator 10 to 16MHz Crystal Oscillator 1 to 10MHz Crystal Oscillator
OSCVHIGH 15 to 25MHz Crystal Oscillator
Input Cells
IPNR IPR2P IPR4P IPR2M IPR4M Input with no pullup/pulldown resistor Input with 2KOhms pullup resistor Input with 100KOhms pullup resistor Input with 2KOhms pulldown resistor Input with 100KOhms pulldown resistor
DSP Macrocell Library
BMA8X8 Mixed Mode multiplier (8 by 8 bits) BMA16X16 Mixed Mode multiplier (16 by 16 bits)
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DESIGN SUPPORT Design Route
I Flexible design route I Proven right first time design Design and layout support for the CLA80k arrays is available from many centres worldwide each of which is connected to our headquarters via high speed data links. A design centre engineer is assigned to each customer's circuit to ensure the best assistance, and a smooth and efficient design flow. Zarlink offers a variety of formal design routes as illustrated in Figure 5. A choice of routes allow for varying levels of customer involvement in a manner which complements individual customers' design styles, whilst maintaining Zarlink's responsibility to ensure first time working devices. The design process incorporates a design audit procedure to verify compliance with customer specification and to ensure manufacturability. The procedure includes four review meetings with the customer held at key stages of the design. Review 1: Held at the beginning of the design cycle to check and agree on performance, packaging, specifications and design timescales. Review 2: Held after Logic Simulation but prior to layout to ensure satisfactory functionality, timing performance, and adequate fault coverage. Review 3: Held after Layout and Post Layout Simulation Verification of satisfactory design performance after insertion of actual track loads. Final check of all device specifications before prototype manufacture. Review 4: Held after Prototype Delivery to confirm that devices meet all specifications and are suitable for full scale production.
CAE Support
I I I I I I I I Synthesis with Synopsys, Mentor or Cadence Sign-off simulation with Mentor or Cadence VIEWlogic VCS simulator supported VITAL compliant library Full top-down design flow support Point tools supported, including Zycad and Powermill Direct route to layout and test Advanced delay modelling and netlist checking
It is Zarlink policy to fully support industry-standard CAE systems that enable a customer to sign off their design without resimulation on a golden simulator. This has the benefit to the customer of not having to learn new tools, and to use the tools they prefer and are familiar with. There is no overhead in engineering effort or time taken rechecking simulation results. Zarlink offers libraries for synthesis tools such as Synopsys, Mentor Autologic II, and Cadence Synergy. This allows a full hierarchical or top-down approach to logic design. The Zarlink's Universal Delay Compiler (UDC) is supplied with all design kits for advanced delay modelling and comprehensive netlist checking. The UDC matches Synopsys and Mentor native delay calculation. The advanced features of the synthesis and simulation tools are used for nonlinear delay modelling for better simulation accuracy. This is implemented for optimum speed depending on the particular tool. Other advanced features are supported where they are available. The information supplied by the customer in the approved CAE vendor format is used as a direct input to the tools that perform the layout and generate the test program.
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SOFTWARE TOOLS
Concept Assessment
RESPONSIBILITY CUSTOMER
DESIGN REVIEW 1
Design capture/compilation or synthesis Improve testability
CUSTOMER AND Zarlink
Testability analysis
INDUSTRY STANDARD DESIGN SOFTWARE AND Zarlink LIBRARIES
Functional simulation
Correct design errors
CUSTOMER OR Zarlink
Test vectors simulation
Improve testability
Zarlink VERIFICATION TOOLS
Zarlink
Netlist handover
DESIGN REVIEW 2 Zarlink OR INDUSTRYSTANDARD LAYOUT TOOLS INDUSTRYSTANDARD SOFTWARE
Place and route Netlist modification
CUSTOMER AND Zarlink
CUSTOMER OR Zarlink
Post-layout simulation
DESIGN REVIEW 3
Prototype manufacture
CUSTOMER AND Zarlink
Zarlink CUSTOMER AND Zarlink Zarlink
APPROVAL
Production
Figure 5 Design Flow
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THERMAL MANAGEMENT
I Low power CMOS for better thermal management I 1.3W per gate per MHz (3V supply) I High pinout power packages available The increase in speed and density available through advanced CMOS processes, results in a corresponding increase in power dissipation. SemiCustom designers now have the ability to design circuits of 260,000 gates and over, and chip power consumption is a very important concern. The logic core of 260k plus gates is the dominant factor in power dissipation at this complexity. It is essential to offer ultra low power core logic to maintain an acceptable overall chip power budget. To minimize this problem Zarlink's CLA80k arrays offer low power factors and a selection of power packages. Dissipation of 1.3W per gate per MHz (3V supply) is lower than most competitive arrays, with the reduced junction temperatures having the added advantage of improved performance and reliability.
ADVANCED DELAY MODELLING
I I I I I Accurate delay calculation Edge speed modelling Pin to pin timings Non-linear delay modelling Accurate delay derating
The accuracy of the delay modelling is demonstrated by the results shown in the table over.
Pin to Pin Delays
Delay models use pin to pin times for both rising and falling delays between each input and output pin.
A B C F
CLA80k POWER DISSIPATION CALCULATION
CLA80k series power dissipation for any array can be estimated by following the example for the CLA87XXX at a typical voltage of 5V. Number of available gates Gates used Gates switching Power dissipation/gate/MHz (W) (gate fanout typically 2 loads, at 5V) Frequency (MHz) Total core dissipation (mW) Number of I/O pads used as Outputs Outputs switching each cycle Dissipation/output buffer/MHz/pF (W) Output loading in pF Output buffer power (mW) Total Power at 10MHz clock rate (W) 157872 40% 15% 4.1 10 388 122 20% 25 50 305 0.7
Figure 6 Path dependent delays The use of pin to pin delays improves simulation accuracy as there can be considerable variation in delay between different input pins. For complex gates (e.g. AND-NOR gates or adders) the variation is up to 40%. For simple NAND and NOR logic gates the typical variation is 20%.
Non-linear curve fitting
Figure 7 and Figure 8 show the rising and falling delay through an inverter. For fast input edges (0.5ns) delay time increases linearly with the output load. For high output loads delay increases linearly with edge speed. Delay for slow input edges and light input loads do not follow the linear model. A simple linear model cannot represent delay accurately. The following equation is used to model delay for CLA80k K 4 Edge Delay = K 1 + K 2 Load + K 3 Edge - ---------------------- K5 Load ------------------ e Edge K1 -Intrinsic delay. The delay with load and input edge speed set to zero. K2 -Delay sensitivity to load. K3 -Delay sensitivity to input edge speed. K4 & K5 - These coefficients reduce the effect of edge for light output loadings.
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Cell 8 stage ripple carry adder 8 stage ripple carry adder 10 NAND2 gates, lightly loaded 10 NAND2 gates mixed heavy then light loading 10 NAND2 gates heavy loading
Conditions Typical process, 5V, 25C Slow process, 4.5V, 70C Slow process, 4.5V, 70 C Slow process, 4.5V, 70C Slow process, 4.5V, 70C
CLA80k delay (ps) 4872 7696 3463 12825 27421
SPICE (ps) 4679 7455 3464 12479 28606
Accuracy 4.0% 3.2% 0.0% 2.8% 4.1%
4.5 4.0 3.5 3.0 Delay (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0 10 20 30 Output Load (LU) Figure 7 Inverter falling delay 4.5 4.0 3.5 3.0 Delay (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0 10 20 30 Output Load (LU) Figure 8 Inverter rising delay 40 50 4.0 2.0 1.0 0.5 12.0 Input edge speed 8.0 40 50 4.0 2.0 1.0 0.5 12.0 8.0 Input edge speed
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Derating for Supply Voltage
Figure 9 shows the increase in gate delay as supply voltage is reduced.
1.8 1.7 1.6 1.5 Derating factor 1.4 1.3 1.2 1.1 1 0.9 0.8 2.5 3 3.5 4 Supply Voltage Figure 9 Derating with supply voltage 4.5 5 5.5
Derating for Temperature
Figure 10 shows the increase in gate delay as the chip junction temperature is increased. It is important to use the junction and not the ambient temperature for worst case simulations 1.3 1.2 1.1 Derating factor 1 0.9 0.8 0.7 0.6 -100 -50 0 50 Temperature Figure 10 Derating with Temperature 100 150
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AC ELECTRICAL CHARACTERISTICS
GATES 2 load units INVX1 NAND2X2 NOR2x2 DF tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL 590 ps 283 ps 528 ps 291 ps 752 ps 249 ps 1068 ps 970 ps 3V 4 load units 889 ps 391 ps 683 ps 398 ps 1065 ps 303 ps 1412 ps 1117 ps 2 load units 421 ps 197 ps 392 ps 200 ps 476 ps 162 ps 689 ps 584 ps 4.5V 4 load units 613 ps 272 ps 490 ps 269 ps 664 ps 205 ps 910 ps 685 ps
INPUTS 2 load units TTL I/P CMOS I/P CMOS SCHMITT tpLH tpHL tpLH tpHL tpLH tpHL 767 ps 704 ps 791 ps 629 ps 1413 ps 1703 ps
3V 4 load units 922 ps 761 ps 872 ps 659 ps 1592 ps 1778 ps 2 load units 708 ps 114 ps 547 ps 433 ps 1114 ps 786 ps
4.5V 4 load units 810 ps 1168 ps 599 ps 454 ps 1223 ps 831 ps
OUTPUT 2 pF 6mA BISTATE 12mA BISTATE 24mA OPEN DRAIN tpLH tpHL tpLH tpHL tpLH tpHL 3615 ps 2472 ps 4672 ps 3814 ps 5500 ps 5011 ps
3V 4 pF 8811 ps 4549 ps 7286 ps 5106 ps 6917 ps 6463 ps 2 pF 2320 ps 1538 ps 2842 ps 2315 ps 3306 ps 2915 ps
4.5V 4 pF 5700 ps 2886 ps 4552 ps 3073 ps 4321 ps 3860 ps
Notes: Assumes worst case process, temperature = 70C, input edge = 0.5 nS
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Output Voltage Static discharge voltage (HBM) Storage Temperature Ceramic Plastic -65 -40 150 125 C C Min. -0.5 -0.5 -0.5 Max. 7.0 VDD+0.5 VDD+0.5 4 Units V V V kV
Exceeding the absolute maximum ratings may cause permanent damage to the device. Extended exposure at the maximum ratings will affect device reliability. HBM stands for Human Body Model.
NORMAL OPERATING CONDITIONS
Neither performance nor reliability is guaranteed outside these limits. Extended operation above these limits may affect device reliability.
PARAMETER Supply Voltage Input Voltage Output Voltage Current per pad Junction Temperature Ambient Temperature Commercial Grade Industrial Grade Military Grade 0 -40 -55 70 85 125 C C C -55 Min. 2.7 VSS VSS Max. 5.5 VDD VDD 100 150 Units V V V mA C
DC ELECTRICAL CHARACTERISTICS
All characteristics are for -55 to150C and 2.7 to 5.5V unless otherwise specified .
Characteristic Sym Min. PDD Operating Power 4.1 Input capacitance Output capacitance Bidirectional capacitance CI COUT CBI 5 6 6 pF pF pF Value Typ. 1.3 Max. W/ MHz VDD = 3V, for NAND2 with 2 standard loads VDD = 5V, for NAND2 with 2 standard loads Any input, excluding package Any output, excluding package Any I/O pin, excluding package Unit Conditions
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Input Characteristics
Characteristic Sym Min. TTL input - IBTTL1 Input low voltage Input high voltage TTL input - IBTTL2 Input low voltage Input high voltage CMOS input - IBCMOS1 Input low voltage Input high voltage CMOS Schmitt - IBST1 Input low voltage Input high voltage Hysteresis TTL Schmitt - IBST2 Input low voltage Input high voltage Hysteresis Low voltage Schmitt - IBST3 Input low voltage Input high voltage Hysteresis Input current or resistance Pullup - IPR2P Pullup - IPR4P Pulldown - IPR2M Pulldown - IPR4M R1 R2 R3 R4 1 50 1 50 2 110 2 110 4 220 4 220 k k k k VIL VIH VH 0.7VDD 80 0.2VDD V V mV VIL VIH VH 2.0 300 0.8 V V mV 2.7 VDD 3.6V VIL VIH VH 0.7VDD 400 0.2VDD V V mV 4.5 VDD 5.5V VIL VIH 0.7VDD 0.2VDD V V 4.5 VDD 5.5V VIL VIH 2.0 0.8 V V 2.7 VDD 5.5V VIL VIH 2.0 0.8 V V 2.7 VDD 3.6V Value Typ. Max. 4.5 VDD 5.5V Unit Conditions
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Output Characteristics
Characteristic Sym Min. High output voltage All outputs OPT1 OPT2 OPT3 OPT6 OPT12 Low output voltage All outputs OPT1 OPT2 OPT3 OPT6 OPT12 High output voltage All outputs OPT1 OPT2 OPT3 OPT6 OPT12 Low output voltage All outputs OPT1 OPT2 OPT3 OPT6 OPT12 VOL VOL VOL VOL VOL VOL VSS-0.05 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 V V V V V V VOH VOH VOH VOH VOH VOH 0.8VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VDD-0.05 0.9VDD 0.9VDD 0.9VDD 0.9VDD 0.9VDD V V V V V V VOL VOL VOL VOL VOL VOL VSS-0.05 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 V V V V V V VOH VOH VOH VOH VOH VOH 0.8VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VDD-0.05 0.9VDD 0.9VDD 0.9VDD 0.9VDD 0.9VDD V V V V V V Value Typ. Max. 2.7 VDD 3.6V IOH = -1A IOH = -0.8mA IOH = -1.6ma IOH = -2mA IOH = -4mA IOH = -8mA 2.7 VDD 3.6V IOL = 1A IOL = 1mA IOL = 2mA IOL = 3mA IOL = 6mA IOL = 12mA 4.5 VDD 5.5V IOH = -1A IOH = -2mA IOH = -4mA IOH = -6mA IOH = -12mA IOH = -24mA 4.5 VDD 5.5V IOL = 1A IOL = 2mA IOL = 4mA IOL = 6mA IOL = 12mA IOL = 24mA Unit Conditions
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Characteristic
Sym Min.
Value Typ. Max.
Unit
Conditions
Tristate output leakage OPT1 OPT2 OPT3 OPT6 OPT12 Tristate output leakage OPT1 OPT2 OPT3 OPT6 OPT12 Output short circuit current OPT1 OPT2 OPT3 OPT6 OPT12 Output short circuit current OPT1 OPT2 OPT3 OPT6 OPT12 Output short circuit current OPT1 OPT2 OPT3 OPT6 OPT12 Output short circuit current OPT1 OPT2 OPT3 OPT6 OPT12 IOS IOS IOS IOS IOS 1.5 3 7 15 30 5 10 15 30 60 10 20 30 60 120 mA mA mA mA mA IOS IOS IOS IOS IOS 5 10 16 32 64 11 22 32 64 128 21 42 64 128 256 mA mA mA mA mA IOS IOS IOS IOS IOS 6 12 19 38 76 12 25 38 76 152 25 50 76 152 304 mA mA mA mA mA IOS IOS IOS IOS IOS 14 28 41 82 164 28 55 82 164 328 55 110 164 328 656 mA mA mA mA mA IOZ IOZ IOZ IOZ IOZ -2 -2 -2 -2 -4 2 2 2 2 4 A A A A A IOZ IOZ IOZ IOZ IOZ -1 -1 -1 -1 -1 1 1 1 1 1 A A A A A
-55 to 100C VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD -55 to 150C VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD VOUT = VSS or VDD 4.5 VDD 5.5V VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD 4.5 VDD 5.5V VDD = max., VO = VSS VDD = max., VO = VSS VDD = max., VO =VSS VDD = max., VO = VSS VDD = max., VO = VSS 2.7 VDD 3.6V VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD VDD = max., VO = VDD 2.7 VDD 3.6V VDD = max., VO = VSS VDD = max., VO = VSS VDD = max., VO = VSS VDD = max., VO = VSS VDD = max., VO = VSS
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QUALITY AND RELIABILITY
I Statistical process control used in manufacture I Regular sample screening and reliability testing I Screening to MIL and other recognized standards At Zarlink quality and reliability are built into the product by statistical control of all of processing operations and by minimizing random uncontrolled effects in all manufacturing operations. Process management involves full documentation of procedures, recording of batch by batch data using traceable procedures. This is preformed using the latest equipment to perform sample screening and conformance testing on finished product. A common information management system is used to monitor the manufacturing of Zarlink CMOS and bipolar processes and operations. All product benefit from the use of this integrated monitoring system resulting in the highest quality standards for all technologies. Further information is contained in the Quality Brochure, available from Zarlink Sales Offices.
PACKAGING
I Wide range of surface mount and through board packages I Ceramic equivalents to most plastic packages for fast prototyping I Ongoing commitment to new package development Packaging Options The package style and pin count information is intended only as a guide. Detailed package specifications are available from Zarlink design centres on request. New packages are being continually introduced, so if a particular package is not listed, please enquire through your Zarlink Sales Representative. The tables below indicate the preferred array size to package combinations. A stock is held of a preferred packages to insure a fast prototype assembly turn around. Alternative array size to package combinations are available, however these packages are not held in stock and extended lead times may adversely affect prototype delivery schedules.
KEY:
1234 1234 Format Number of Preferred Array/Qualified Package Combination Format Number of Physical Fit only - requires Marketing approval prior to quotation
1234* 1234^
In development Maximum number of ceramic prototypes is 10 ONLY NO footprint compatible ceramic prototypes are available
Note: Package dimensions implicit in the `Code' description, pitch and height dimensions are for guidance only and therefore are approximate.
16
HIGH DENSITY PAD ARRAY PRODUCTION PACKAGING OPTIONS
Metric Quad Flat Pack - plastic. Style Leads 44 52 64 M Q F P 64 64 80 80 100 120 128 144 160 Code MQFP44-GP1010 MQFP52-GP1010 MQFP64- GP1420 MQFP64-GP1414 MQFP64-GP1414 MQFP80-GP1420 MQFP80-GQ1414 MQFP100GP-1420 MQFP120GP-2828 MQFP128GP-2828 MQFP144GP-2828 MQFP160GP-2828 Pitch 0.80 0.65 1.00 0.80 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65 Height 2.0 2.0 2.8 2.8 2.0 2.8 2.0 2.8 3.4 3.4 3.4 3.4 81 2152 1710 1755 1835^ 2172^ 2157 1807^ 2166 82 2152 1710 1755 1835^ 2172^ 2157 1807 2166 1730^ 2100^ 2159^ 83 2152 1710 1755 1835^ 2172^ 2157 1807 2166 1899 2100 2159^ 1882^ 84 2152 1710 1755 1835 2172 2157 1807 2158 1899 2100 2159 1882^ 2172 2157 1807 2158 1899 2100 2159 1882^ 1808 2158 1899 2100 2159 1882 1882 2118^ 1732 1713^ 2172 1710^ 1755 85 86 87 88 89
FQFP (Fine Pitch) - plastic. Style F Q F P Leads 100 208 240 304 Code Pitch Height 2.0 3.4 3.4 3.8 81 1810 82 1810 83 1810 84 2156 2160^ 85 2156 2160^ 86 2156^ 2160^ 2160 2163^ 2163 1880^ 87 88 89
FQFP100-FP0.50 1414 FQFP208-FP0.50 2828 FQFP240-FP0.50 3232 FQFP304-FP0.50 4040
LQFP (Low profile) - plastic. Style Leads 48 L Q F 64 80 100 Code LQFP48-FP0707 LQFP64-FP1010 LQFP80- GP1414 LQFP100-FP1414 Pitch 0.50 0.50 0.65 0.50 Height 1.4 1.4 1.4 1.4 81 2168^ 2130 1889 1887 82 2168^ 2130 1889 1887 2130 1889 1887 2130^ 1889 1888 2130^ 1889 1888 1888 83 84 85 86 87 88 89
17
P
144 176
LQFP144-FP2020 LQFP176-FP2424
0.50 0.50
1.4 1.4
2164^
2164^ 2165^
2164^ 2165^
2164 2165^
2164 2165^
2237 2165
2237^
PLCC (Plastic J - Leaded Chip Carrier). Style P L C C Leads 28 44 68 84 Code PLCC28-HP1212 PLCC44-HP1717 PLCC68-HP2525 PLCC84-HP3030 Pitch 1.27 1.27 1.27 1.27 Height 4.57 4.57 5.08 5.08 81 1613 1491 1659 1660 82 1613 1491 1659 1660 83 1613 1491 1659 1660 84 1629 1491 1659 1660 1660 1491 85 86 87 88 89
PSOP (Plastic Small Outline package). Style P S O P Leads 16 20 24 28 Code PSOP16-MP0811 PSOP20-MP0813 PSOP24-MP0816 PSOP28-MP0818 Pitch 1.27 1.27 1.27 1.27 Height 2.64 2.64 2.64 2.64 81 1575 1583 1587 1768 1768^ 82 83 84 85 86 87 88 89
P2QFP (`PowerQuad 2') - plastic with copper heat slug. Style Leads 100 P 2 Q F P 120 128 144 160 208 240 304 Code P2QFP100GH-1420 P2QFP120GH-2828 P2QFP128GH-2828 P2QFP144GH-2828 P2QFP160GH-2828 P2QFP208GH-2828 P2QFP240GH-3232 P2QFP304GH-4040 Pitch 0.65 0.80 0.80 0.65 0.65 0.50 0.50 0.50 Height 2.8 3.4 3.4 3.4 3.4 3.4 3.4 3.4 81 82 2202 83 2202 3002 2221 2222^ 2223^ 84 2202 3002 2221 2222 2223^ 85 2202 3002 2221 2222 2223 3002 2221 2222 2223 2225^ 2200 2221^ 2222 2223^ 2225 2200^ 2203^ 2226^ 2196^ 2218 2229 2219^ 2218^ 2229 2219^ 86 87 88 89
18
HIGH DENSITY PAD ARRAY PROTOTYPING PACKAGING OPTIONS
Important: CQFP/CSOP is for prototyping only, it is not available for production.
Prototypes for MQFP's and P2 & P4 MQFP's. Style Leads 44 52 64 C Q F P 64 80 80 100 120 128 144 160 Code CQFP44-GG1010 CQFP52-GG1010 CQFP64- GG1420 CQFP64-GG1414 CQFP80-GG1420 CQFP80-GG1414 CQFP100GG-1420 CQFP120GG-2828 CQFP128GG-2828 CQFP144GG-2828 CQFP160GG-2828 Pitch 0.80 0.65 1.00 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65 Height 3.2 3.2 2.8 2.8 2.8 2.8 2.8 3.6 3.6 3.6 3.6 1740 2102 1865 1736 1740 2102 1865 1736 1740 2102 1865 1736 1861 81 1735 1800 1773 82 1735 1800 1773 83 1735 1800 1773 84 1799 1800 1773 2169 1740 2102 1865 1736 1861 1816 1772 2169 1771 2102 1865 1736 1861 1816 1863 1864 1737 1861 1816 1769 1770 1769 1737 2169 85 86 87 88 89
"Prototypes for FQFP, LQFP & P2 MQFP's. " Style Leads 64 C Q F P 100 144 176 208 240 304 Code CQFP64-FG1010 CQFP100FG-1414 CQFP144FG-2020 CQFP176FG-2424 CQFP208FG-2828 CQFP240FG-3232 CQFP304FG-4040 Pitch 0.50 0.50 0.65 0.50 0.50 0.50 0.50 Height 3.2 2.8 3.6 3.77 3.6 3.6 3.6 81 2103 1860 82 2103 1860 83 2103 1860 1860 2104 1860 2104 2101 2104 2217 2217 2141 2141 2143 2144 84 85 86 87 88 89
19
Prototypes for PLCC Style C c L C C Leads 28 44 68 84 Code CcLCC28-HC1212 CcLCC44-HC1717 CcLCC68-HC2525 CcLCC84-HC3030 Pitch 1.27 1.27 1.27 1.27 Height 4.11 3.43 3.43 3.43 81 1623 1453 1625 1626 82 1623 1453 1625 1626 83 1623 1453 1625 1626 84 1623 1453 1625 1626 1626 1453 85 86 87 88 89
Prototypes for PSOP Style C S O P Leads 16 20 24 28 Code CSOP16-MC0811 CSOP20-MC0813 CSOP24-MC0816 CSOP28-MC0818 Pitch 1.27 1.27 1.27 1.27 Height 2.75 2.75 2.75 2.75 81 1697 1698 1699 1875 82 83 84 85 86 87 88 89
20
STANDARD DENSITY PAD ARRAY PACKAGING OPTIONS, MILITARY ARRAYS
PLCC Style C c L C C Leads 68 84 Code CcLCC68-HC-2525 CcLCC84-HC-3030 Pitch 1.27 1.27 Height 3.43 3.43 MLA85 1621 1626 MLA87 MLT88 MLT89
LdCC Style L d C C Leads 132 172 196 Code LdCC132-GCA-2424 LdCC172-GCA-3030 LdCC196-GCA-3535 Pitch 0.635 0.635 0.635 Height 2.57 2.82 2.82 MLA85 1840 MLA87 1662 1668 1672 1680 1831 MLT88 MLT89
LdCC & TLdCC (Power) Style L d C C T L d Leads 132 172 196 256 132 172 320 Code LdCC132-GCP-2424 LdCC172-GCP-3030 LdCC196-GCP-3535 LdCC256-GCP-3737 TLdCC132-YCP-2424 TLdCC172-YCP-3030 TLdCC320-YCP-4444 Pitch 0.635 0.635 0.635 0.51 0.62 0.62 0.5 Height 3.33 3.58 3.58 3.66 3.33 3.61 2.64 MLA85 2146 MLA87 1841 1836 1839 1762 1739 1834 2127 2215 2206 2205 2147 1832 MLT88 MLT89
PGA Style Leads 84 100 P G A 120 144 180 181 257 Code PGA84-ACA-2828 PGA100-ACA-3434 PGA120-ACA-3434 PGA144-ACA-4040 PGA180-ACA-4040 PGA181-ACA-4040 PGA257-ACA-5151 Pitch 2.54 2.54 2.54 2.54 2.54 2.54 2.54 Height 4.14 4.14 4.14 4.14 4.14 4.14 4.14 MLA85 1479 1480 1481 MLA87 1671 1465 1466 1483 1484 1844 1824 2149 MLT88 MLT89
PGA (Power) Style P G A (P) Leads 84 144 208 209 Code PGA(P)84-ACB-2828 PGA(P)144-ACB-4040 PGA(P)208-ACB-4545 PGA(P)209-ACB-4545 Pitch 2.54 2.54 2.54 2.54 Height 6.15 6.15 4.45 4.45 1811 2151 MLA85 MLA87 1815 1812 MLT88 1692 1693 1838 2148 2145 MLT89
21
NOTES
22
NOTES
23
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